1. Field of the Invention
The present invention relates to integrated circuit design, and more specifically to a method and apparatus for generating multiple delayed signals of different phases from a reference signal using DLLs.
2. Related Art
There is often a need to generate multiple delayed signals of different phases from a reference signal. For example, in analog to digital converters (ADCs), there is often a need to generate a sampling signal and a hold signal, which have some overlapping logic low level and yet have non-overlapping logic high level, and the timings of the edges for the corresponding signals may be derived from the edges of the delayed signals.
Delay locked loop (DLL) is often used to generate such delayed signals of different phases from a reference clock signal as described with the example circuit of FIG. 1. There is shown DLL 100 containing delay elements 110A-110X, phase detector 130, charge pump 140, and capacitor 160. Each component is described in further detail below.
Delay elements 110A-110X are connected in series, and each element generally offers equal delay. The magnitude of the delay is determined by the voltage level on path 161. A reference clock signal of clock period (T) is received on path 101, and the signal is ideally delayed by a magnitude equaling (T/X) by each delay element. Thus, the output of the Nth delay element is delayed by a factor of (N*T/X). Accordingly, the output of the last delay element and the reference signal should ideally have the same phase and frequency, and the corresponding propagated edges should be with a time difference of T only, as depicted in FIG. 2.
FIG. 2 is a timing diagram illustrating the operation of a DLL circuit assuming there are only three delay elements. The reference clock signal, the first delayed clock signal (i.e., output of the first delay element, e.g., 110A), the second delayed clock signal and the third delayed clock signal are respectively shown as signals 101, 220, 230 and 113. As shown by the corresponding rising edges, signals 220, 230 and 113 respectively lag reference signal 101 by ⅓ time period, ⅔ time period and 3/3 time period (T). The manner in which the remaining elements of DLL circuit of FIG. 1 operate to control the delay elements, to provide at least some of such features, is described below in further detail.
Continuing with reference to FIG. 1 again, phase detector 130 compares the phases of reference clock signal 101 on one input and final delayed signal 113, and controls charge pump 140 to either charge or discharge capacitor 160 depending on the comparison result. For example, capacitor 160 may be charged more if final delayed signal 113 is deemed to lag reference signal 101, and discharged if reference signal 101 is deemed to lag final delayed signal 113.
The voltage across capacitor 160 controls the amount of delay caused by each of the delay elements 110A-110X. In one embodiment, an increase in the voltage/charge increases the magnitude of the delay. Thus, due to the operation of phase detector 130, the rising edges of signals 101 and 113 are synchronized in the steady state.
One problem with the above approach is that the rising edges may be synchronized to multiples of time period T since phase detector 130 may not recognize if the rising edges are off by more than 1.5 T (in general). Such a problem is addressed by another prior embodiment described below with reference to FIG. 3.
FIG. 3 is a circuit diagram illustrating the details of another prior DLL circuit generating multiple delayed signals of different phases from a reference signal. For conciseness, only the changes in relation to the circuit diagram of FIG. 1 are shown. Also, the circuit is described in further detail in a paper entitled, “CMOS DLL-based 2-V 3.2 ps Jitter 1-GHz Clock Synthesizer and Temperature-Compensated Tunable Oscillator” by Foley et al, and published in IEEE Journal of Solid State Circuits, Vol. 36, No. 3, March 2001 (Hereafter “Foley”).
DLL circuit 300 of FIG. 3 is shown containing delay elements 110A-110X, phase detector 330, charge pump 140, lock detector 350, and capacitor 160. Lock detector 350 generally indicates situations in which the aggregate delay of the delay elements exceeds a pre-specified upper threshold or falls below a pre-specified lower threshold. Comparison with upper thresholds avoids the delayed signals locking to multiples of the time period of the reference signal. Comparison with lower threshold ensures that attempts to (erroneously) lock towards 0 phase delay is avoided.
Thus, lock detector 350 examines the outputs of delay elements 110A-110X, and generates signals indicating false locks (i.e., time period is of signals 101 and 113 is a multiple of an integer greater than or equal to 2). Accordingly, phase detector 330 continues with adjusting the phase until lock detector 350 does not indicate false locks and the rising edges of signals 101 and 113 are synchronized.
One limitation of the circuit of FIG. 3 is that the input reference signal 101 needs to have a duty cycle (Ton/T, wherein Ton represents the duration of logic high and T represents the time period) of at least approximately 50% since otherwise challenges may be presented in recognizing the conditions (noted above) sought to be detected.
FIG. 4 depicts another prior embodiment which overcomes such a disadvantage of FIG. 3. Again, for conciseness, the differences in relation to FIG. 3 only are shown. DLL circuit 400 is shown containing delay elements 110A-110X, duty cycle correction circuit (DCC) 420, phase detector 330, charge pump 140, lock detector 350, and capacitor 160.
DCC 420 operates to generate a modified reference signal having a duty cycle of 50% from reference signal 401if the duty cycle is not equal to 50%. Such modified reference signal is provided on path 101 to both phase detector 330 and delay element 110A. DCC 420 is implemented using well-known approaches.
One problem with the approach of FIG. 4 is that additional delay is introduced in the signal path, thereby causing output of delay element 110A to have (T/X+Tdcc), wherein T/X is described above and Tdcc represents the delay of DCC 420. Such additional delay (Tdcc) may be undesirable in several environments (particularly requiring high throughput performance). In addition, any jitter in DCC 420 adds to the signal path.
In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit (s) in the corresponding reference number.